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 INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT30 8-input NAND gate
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
8-input NAND gate
FEATURES * Output capability: standard * ICC category: SSI GENERAL DESCRIPTION
74HC/HCT30
The 74HC/HCT30 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT30 provide the 8-input NAND function. QUICK REFERENEC DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay A, B, C, D, E, F, G, H to Y input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 12 3.5 15 HCT 12 3.5 15 ns pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
8-input NAND gate
PIN DESCRIPTION PIN NO. 1 2 3 4 5 6 7 8 9, 10, 13 11 12 14 SYMBOL A B C D E F GND Y n.c. G H VCC data input data input data input data input data input data input ground (0 V) data output not connected data input data input positive supply voltage NAME AND FUNCTION
74HC/HCT30
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-input NAND gate
74HC/HCT30
Fig.4
Functional diagram; Y = ABCDEFGH.
Fig.5 Logic diagram.
FUNCTION TABLE INPUTS A L X X X X X X X H Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care B X L X X X X X X H C X X L X X X X X H D X X X L X X X X H E X X X X L X X X H F X X X X X L X X H G X X X X X X L X H H X X X X X X X L H OUTPUT Y H H H H H H H H L
December 1990
4
Philips Semiconductors
Product specification
8-input NAND gate
DC CHARACTERISTICS FOR 74 HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI
74HC/HCT30
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to + 85 -40 to +125 UNIT V CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS TEST CONDITIONS
min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay A, B, C, D, E, F, G, H to Y output transition time 41 15 12 19 7 6 130 26 22 75 15 13 165 33 28 95 19 16 195 39 33 110 22 19 Fig.6
tTHL/ tTLH
ns
Fig.6
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT A, B, C, D, E, F, G, H UNIT LOAD COEFFICIENT 0.60
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to + 85 -40 to +125 UNIT V CC (V) WAVEFORMS TEST CONDITIONS
min. typ. max. min. max. min. max. tPHL/ tPLH tTHL/ tTLH propagation delay A, B, C, D, E, F, G, H to Y output transition time 16 7 28 15 35 19 42 22 ns ns 4.5 4.5 Fig.6 Fig.6
December 1990
5
Philips Semiconductors
Product specification
8-input NAND gate
AC WAVEFORMS
74HC/HCT30
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the input (A, B, C, D, E, F, G, H) to output (Y) propagation delays and the output transition times.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
6


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